Heretofore in this field, it has proven difficult to make electrical connection to small features on an integrated circuit. Because of the small feature size, conventional techniques for defining such metal connections must rely on very tight alignment tolerances during photolithography and use insulating materials to reduce shorting that results from slight misalignments. These techniques limit the ability to scale small features, and decrease yield and throughput. The use of insulating materials also increases the capacitance between the metal connection and other features, which is undesirable in many applications.